Embodiments of the present invention relate to integrated circuits and the processing for the manufacture of semiconductor devices. More particularly, embodiments of the present invention provide a method and device for providing a dual-gate FinFET and a tri-gate FinFET on the same SOI substrate. Merely by way of example, the invention has been applied to high current drive I/O devices and low leakage core logic devices in integrated circuits. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to integrated circuits requiring devices having different threshold voltages and performance requirements.
As semiconductor device feature size continues to scale down to nanometer regime and approaches scaling limits for CMOS processes and technology, at such reduced gate lengths, conventional CMOS devices have difficulty in maintaining high drive current (Ion) with low leakage (Ioff) and threshold stability. To fabricate devices beyond current scaling limits, integrated circuit manufacturers are rigorously exploring alternative gate stack materials, band engineering methods, and alternative transistor structures simultaneously.
CMOS designs below 100 nm are severely constrained by lateral short channel effect (SCE) and vertical gate insulator tunneling leakage current. One of the approaches to circumvent the gate tunneling restriction is to change the device structure in such a way that MOSFET gate length can be scaled down further even with thicker oxide. A promising candidate for channel length range of 5-30 nm is the so-called FinFET built on an SOI substrate.
In low power circuit applications, there is often a need to have transistors having different threshold voltages on the same chip. For example, certain circuits need low threshold voltage for higher drive current and can tolerate higher leakage current, whereas other circuits may demand low leakage current which requires a high threshold current. In conventional technologies, it is necessary to fabricate transistors having different gate oxide thicknesses and channel dopings to obtain multiple different threshold voltages.
For small geometry MOSFET devices, silicon-on-insulator (SOI) technology has been proposed as an alternative to bulk CMOS devices. SOI MOSFET devices are fabricated in a thin film of silicon layer overlying an insulating layer. Such devices often offer reduced parasitic effect than conventional bulk devices. Further improvement can be obtained in a FinFET in which a gate electrode is formed over the sides and the top of a channel region of an MOSFET. The channel region, along with a source region and a drain region are formed in a silicon fin structure located over an insulator. In a FinFET, the gate electrode has a better control of the channel region. In some examples, a FinFET device includes a gate electrode that is formed over three sides of a channel region. It is referred to as a Tri-gate FinFET or single-gate FinFET. In other examples, a FinFET device can have two independent gate electrodes. It is referred to as a dual-gate FinFET. In conventional technology, Tri-gate and dual-gate FinFETs are fabricated separately for different applications. These and other limitations are described throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.